Modern computer systems are typically formed of many semiconductor components that can communicate together via various interconnects such as present on a circuit board. One common such interconnect mechanism, e.g., for incorporating peripheral devices such as a graphics card, is a Peripheral Component Interconnect Express (PCIe™) protocol in accordance with links based on the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereafter the PCIe™ Specification). Such an interconnect can be formed of multiple layers, including a transaction layer, a link layer, and a physical layer.
To reduce power consumption when communications are not occurring on a given interconnect, various mechanisms can be provided. If no communications are likely to occur for some time, the interconnect can be placed in a low power state in which various interconnect circuitry is disabled.
To determine when impending PCIe™ traffic is about to occur when in an idle/sleep condition, squelching is a PCIe™ physical layer input/output (I/O) function to detect such traffic. Squelch logic attempts to detect voltage in receive pins of the interconnect to sense activity and prepare a link layer transaction state machine for proper operation to exit from the electrical state (EL) or lower power state. The squelch logic in the I/O circuit typically includes analog differential amplifiers, integrators and other miscellaneous digital logic. However, such squelch logic can consume significant power, as typically the squelch logic is provided for each lane of an interconnect. As the number of lanes increases, so too does the total squelch power, which can manifest as a substantial portion of the idle power budget, particularly in the low power market.